S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 88

Manufacturer Part Number

S912XEQ384J3MALR

S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112

Manufacturer

Freescale Semiconductor

Chapter 1 Device Overview MC9S12XE-Family

The XCLKS is an input signal which controls whether a crystal in combination with the internal loop

controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock

circuitry is used. For this device XCLKS is mapped to PE7.

The XCLKS signal selects the oscillator conﬁguration during reset low phase while a clock quality check

is ongoing. This is the case for:

The selected oscillator conﬁguration is frozen with the rising edge of the RESET pin in any of these above

described reset cases.

Power on reset or low-voltage reset

Clock monitor reset

Any reset while in self-clock mode or full stop mode

Oscillator Conﬁguration

Figure 1-10. Loop Controlled Pierce Oscillator Connections (XCLKS = 1)

Figure 1-11. Full Swing Pierce Oscillator Connections (XCLKS = 0)

Figure 1-12. External Clock Connections (XCLKS = 0)

MC9S12XE-Family Reference Manual Rev. 1.24

Not Connected

speciﬁed by crystal vendor

Ceramic Resonator

CMOS-Compatible

External Oscillator

Ceramic Resonator

Freescale Semiconductor