S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 537

Manufacturer Part Number

S912XEQ384J3MALR

S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112

Manufacturer

Freescale Semiconductor

Read or write: Anytime

All bits reset to zero.

Freescale Semiconductor

Module Base + 0x0003

Module Base + 0x0004

Output Compare Mask Action for Channel 7:0

A channel 7 event, which can be a counter overﬂow when TTOV[7] is set or a successful output compare

on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,the output compare

action reﬂects the corresponding OC7D bit.

0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on

1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a

Note: The corresponding channel must also be setup for output compare (IOSx = 1 andOCPDx = 0) for data to

Output Compare 7 Data Bits — A channel 7 event, which can be a counter overﬂow when TTOV[7] is set or A

channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data

Output Compare 7 Data Register (OC7D)

Timer Count Register (TCNT)

a channel 7 event, even if the corresponding pin is setup for output compare.

channel 7 event.

be transferred from the output compare 7 data register to the timer port.

Figure 14-6. Output Compare 7 Data Register (OC7D)

Figure 14-7. Timer Count Register High (TCNT)

MC9S12XE-Family Reference Manual Rev. 1.24

Table 14-4. OC7M Field Descriptions

Table 14-5. OC7D Field Descriptions

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)