S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 616

Manufacturer Part Number

S912XEQ384J3MALR

S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112

Manufacturer

Freescale Semiconductor

Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)

The CANBTR1 register conﬁgures various CAN bus timing parameters of the MSCAN module.

1. Read: Anytime

Module Base + 0x0003

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Sampling — This bit determines the number of CAN bus samples taken per bit time.

0 One sample per bit.

1 Three samples per bit

If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If

SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit

rates, it is recommended that only one sample is taken per bit time (SAMP = 0).

Time Segment 2 — Time segments within the bit time ﬁx the number of clock cycles per bit time and the location

of the sample point (see

Time Segment 1 — Time segments within the bit time ﬁx the number of clock cycles per bit time and the location

of the sample point (see

MSCAN Bus Timing Register 1 (CANBTR1)

Figure 16-7. MSCAN Bus Timing Register 1 (CANBTR1)

Table 16-6. Synchronization Jump Width (continued)

Table 16-8. CANBTR1 Register Field Descriptions

MC9S12XE-Family Reference Manual Rev. 1.24

Table 16-7. Baud Rate Prescaler

16-44). Time segment 2 (TSEG2) values are programmable as shown in

16-44). Time segment 1 (TSEG1) values are programmable as shown in

Synchronization Jump Width

Prescaler value (P)

2 Tq clock cycles

3 Tq clock cycles

4 Tq clock cycles

Access: User read/write

Freescale Semiconductor