S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 903

• Manufacturer Part Number: S912XEQ384J3MALR
• Description: S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
• Manufacturer: Freescale Semiconductor

25.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Freescale Semiconductor
FDIV[6:0]
FDIVLD
Address
Offset Module Base + 0x0000
Reset
& Name
Field
6–0
7
W
R
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms.
Please refer to
Flash Clock Divider Register (FCLKDIV)
0
7
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
= Unimplemented or Reserved
7
Section 25.4.1, “Flash Command Operations,”
Figure 25-4. FTM256K2 Register Summary (continued)
0
6
Figure 25-5. Flash Clock Divider Register (FCLKDIV)
= Unimplemented or Reserved
Table 25-9
MC9S12XE-Family Reference Manual Rev. 1.24
6
Table 25-8. FCLKDIV Field Descriptions
0
5
shows recommended values for FDIV[6:0] based on OSCCLK frequency.
5
CAUTION
0
4
Description
4
FDIV[6:0]
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1)
0
3
for more information.
3
0
2
2
0
1
1
0
0
0
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