S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 121

• Manufacturer Part Number: S912XEQ384J3MALR
• Description: S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
• Manufacturer: Freescale Semiconductor

1. Read: Anytime.
2.3.21
Freescale Semiconductor
Function
Address 0x0240
Write: Anytime.
DDRK
Altern.
Field
Field
Reset
PTT
PTT
PTT
7-0
7-6
4-0
5
W
R
Port K Data Direction—
This register controls the data direction of pins 7 through 0.
The external bus function controls the data direction for the associated pins. In this case the data direction bits will
not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
Port T general purpose input/output data—Data Register
Port T pins 7 through 0 are associated with ECT channels IOC7 and IOC6.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port T general purpose input/output data—Data Register
Port T pins 5 is associated with ECT channel IOC5 and the VREG_API output.
The ECT function takes precedence over the VREG_API and the general purpose I/O function if the related channel
is enabled.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port T general purpose input/output data—Data Register
Port T pins 4 through 0 are associated with ECT channels IOC4 through IOC0.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
PTT7
IOC7
Port T Data Register (PTT)
—
0
7
PTT6
IOC6
—
0
6
Table 2-19. DDRK Register Field Descriptions
Table 2-20. PTT Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.24
Figure 2-19. Port T Data Register (PTT)
VREG_API
PTT5
IOC5
0
5
PTT4
IOC4
—
0
4
Description
Description
PTT3
IOC3
—
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
PTT2
IOC2
—
0
2
Access: User read/write
PTT1
IOC1
—
0
1
PTT0
IOC0
—
0
0
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