S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 218

Manufacturer Part Number

S912XEQ384J3MALR

S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112

Manufacturer

Freescale Semiconductor

Chapter 3 Memory Mapping Control (S12XMMCV4)

The arbitration scheme allows only one master to be connected to a target at any given time. The following

rules apply when prioritizing accesses from different masters to the same target bus:

CALL and RTC instructions are uninterruptable CPU instructions that automate page switching in the

program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is

CPU always has priority over BDM and XGATE.

XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU

for its duration.

XGATE has priority over BDM.

BDM has priority over CPU and XGATE when its access is stalled for more than 128 cycles. In the

later case the suspect master will be stalled after ﬁnishing the current operation and the BDM will

gain access to the bus.

In emulation modes all internal accesses are visible on the external bus as well and the external bus

is used during access to the PRU registers.

Initialization/Application Information

CALL and RTC Instructions

Master Bus Prioritization regarding access conﬂicts on Target Buses

MC9S12XE-Family Reference Manual Rev. 1.24

Figure 3-23. MMC Block Diagram

MMC “Crossbar Switch”

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