PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 91

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

0
0
1
5.2.1.3 PCM Interface Characteristics
In the following the PCM interface characteristics that can be programmed in the PCM
interface registers are explained in more detail.
PCM Mode PMOD: PMD1, PMD0
The PCM mode primarily defines the actual number of PCM highways that can be used
for switching purposes (logical ports). 1, 2, or 4 logical PCM ports can be selected. Since
the channel capacity of the EPIC is constant (128 channels per direction), the PCM
mode also influences the maximum possible data rate. In each PCM mode a minimum
data rate as well as a minimum data rate stepping are specified.
It should also be noticed that there are some restrictions concerning the PCM to CFI data
rate ratio which may affect some applications. These restrictions are described in
chapter 5.2.2.3.
The table below summarizes the specific characteristics of each PCM mode (DR = PCM
data rate):
Table 8
PMD1
Note: The label is used to specify a PCM port (logical port) when programming a
PCM Clock Rate PMOD:PCR
The PCM interface is clocked via the PDC pin. If PCR is set to logical 0, the PDC
frequency must be identical to the selected data rate (single clock operation). If PCR is
set to logical 1, the PDC frequency must be twice the selected data rate (double clock
operation).
Note: In PCM mode 2, only single clock rate operation is allowed.
In PCM mode 0 for example, PCR can be set to 1 to operate at up to four 2.048 MHz
PCM highways with a PCM clock of 4.096 MHz.
Semiconductor Group
switching function. It should not be confused with the physical port number which
refers to actual hardware pins. The relationship between logical and physical port
numbers is given in table 13 and is illustrated in figure 28.
PMD0 PCM
0
1
0
Mode
0
1
2
Number (Label)
of Logical Ports
4 (0 … 3)
2 (0 … 1)
1
91
256
512
1024
min. max.
Data Rate
[kbit/s]
2048
4096
8192
Data Rate
Stepping
[kbit/s]
256
512
1024
Application Hints
PDC
Frequency
(Clock Rate)
DR, 2
DR, 2
DR
PEB 2055
PEF 2055
DR
DR