PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 32

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

The selection is performed via pin ALE as follows:
The occurrence of an edge on ALE, either positive or negative, at any time during the
operation immediately selects interface type (3). A return to one of the other interface
types is only possible by issuing a hardware reset.
In order to simplify the use of 8- and 16-bit Siemens / Intel type CPUs, different register
addresses are defined in multiplexed and demultiplexed bus mode (see chapter 4.1). In
the multiplexed mode even addresses are used (AD0 always 0).
For a demultiplexed P interface mode the OMDR:RBS bit is needed in addition to the
address lines A3 .. A0. With OMDR:RBS (register bank selection) one of two register
banks is selected.
RBS = “1” selects a set of registers used for device initialization (e.g. CFI and PCM
interface initialization).
RBS = “0” switches to a group of registers necessary during operation (e.g. connection
programming).
The OMDR register containing the RBS bit can be accessed with either value of RBS.
3
The EPIC, designed as a flexible line-card controller, has the following main
applications:
– Digital line cards, with the CFI typically configured as IOM-2, IOM-1 (MUX) or SLD.
– Analog line cards, with the CFI typically configured as IOM-2 or SLD.
– Key systems, where the EPIC’s ability to mix CFI configurations is utilized.
To operate the EPIC the user must be familiar with the device’s microprocessor
interface, interrupt structure and reset logic.
3.1
The EPIC is programmed via an 8-bit parallel interface that can be selected to be
Semiconductor Group
(1) Motorola type, with control signals DS, R/W and CS.
(2) Siemens / Intel non-multiplexed bus type, with control signals WR, RD
(3) Siemens / Intel multiplexed address/data bus type, with control signals
ALE tied to
ALE tied to
Edge on ALE
and CS.
ALE, WR, RD, and CS.
Operational Description
Microprocessor Interface Operation
V
V
DD
SS
(1)
(2)
(3)
32
Operational Description
PEB 2055
PEF 2055