PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 156

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

PEB 2055
PEF 2055
Application Hints
5.4.2
Subchannel Switching
The switching of subchannels is programmed by first specifying the time slot (which is
always 8 bits wide) to be switched, then by restricting the actual switching operation to
the desired bandwidth and subtime slot position. The switching function for an (8 bit) CFI
time slot is programmed in the control memory (CM) by writing a pointer that points to
an (8 bit) PCM time slot to the corresponding data field location. The MADR register
contains the pointer (PCM time slot) and the MAAR register is used to specify the CFI
time slot.
The “8 bit” connection can now be restricted to the desired 4 or 2 bit connection by
selecting an appropriate control memory code. The code is programmed via
MACR:CMC3 … 0. These subchannel codes perform two functions: they specify the
bandwidth (actual number of bits to be switched) and the location of the subtime slot
within the selected (8 bit) PCM time slot. The location of the subtime slot within the
selected (8 bit) CFI time slot is predefined by the setting of the CSCR register. Each CFI
port can be set to a different subtime slot mode. In each mode a certain relationship
exists between programmed bandwidth (which can still be individually selected for each
CFI time slot) and the occupied bit positions within the time slot (which is fixed for each
CFI port by the CSCR register).
It should be noted that only one subtime slot can exist within a given CFI time slot. On
the PCM side however each time slot may be split up into 2
4 bits, 4
2 bits or any
mixture of these.
The CSCR register has the following format:
CFI Subchannel Register
read/write
reset value:
00
H
bit 7
bit 0
CSCR
SC31
SC30
SC21
SC20
SC11
SC10
SC01
SC00
Below, all possible combinations of subchannel switching between the CFI and PCM
interfaces are shown:
Semiconductor Group
156