PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 241

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

Card
The following values must be programmed to the PCM and CFI registers of the EPIC
and to the MOD and CFR registers of the MUSAC to obtain the desired PCM and IOM-2
timing:
EPIC
PBNR
POFD
POFU
PCSR
CMD1
CMD2
CBNR
Figure 85
Timing Example to Interconnect the EPIC
PMOD
Semiconductor Group
®
MUSAC/EPIC :
SP/PFS
CLK/PDC
OUT#/TxD#
IN#/RxD#
= 0100 0100
= 1111 1111
= 1111 0000
= 0001 1000
= 0100 0101
= 0010 0000
= 1101 0000
= 1111 1111
R
TS63, Bit 0
TS63,
Bit 0
B
B
B
B
B
B
B
B
= 44
= FF
= F0
= 18
= 45
= 20
= D0
= FF
TS0,
TS0, Bit 7
Bit 7
H
H
H
H
H
H
H
H
PCM mode 1, single rate clock, PFS
evaluated with falling clock edge, input
selection RxD0 and RxD3, PCM comparison
disabled
512 bits (64 ts) per PCM frame
PFS marks downstream PCM TS0, bit 6
PFS marks upstream PCM TS0, bit 6
PCM data received with falling, transmitted
with rising clock edge
PDC/PFS clock source, PFS evaluated with
falling clock edge, prescaler = 1, CFI mode 0
FC mode 6, double rate clock, CFI data
transmitted with rising, received with falling
clock edge
256 bits (32 ts) per CFI frame
241
TS0, Bit 6
TS0,
®
Bit 6
and the MUSAC
TS0, Bit 5
TS0,
Bit 5
TS0, Bit 4
TS0,
on an IOM
Bit 4
Application Hints
TS0, Bit 3
TS0,
Bit 3
PEB 2055
PEF 2055
®
-2 Line
ITT09557