PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 39

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

Time slot switching is always carried out on 8-bit time slots, the actual position and
number of transferred bits can however be limited to 4-bit or 2-bit sub time slots within
these 8-bit time slots. On the CFI side, only one sub time slot per 8-bit time slot can be
switched, whereas on the PCM-interface up to 4 independent sub time slots can be
switched.
Examples are given in chapter 5.3.
Sub Time Slot Switching
Sub time slot positions at the PCM-interface can be selected at random, i.e. each single
PCM time slot may contain any mixture of 2- and 4-bit sub time slots. A PCM time slot
may also contain more than one sub time slot. On the CFI however, two restrictions must
be observed:
– Each CFI time slot may contain one and only one sub time slot.
– The sub-slot position for a given bandwidth within the time slot is fixed on a per port
For more detailed information on sub-channel switching please refer to chapter 5.4.2.
Switching paths 3 and 4 of figure 18 can be realized for all available time slots. Path 3
can be implemented by defining the corresponding CFI time slots as “ P channels” or as
“pre-processed channels”.
Each single time slot can individually be declared as “ P channel”. If this is the case, the
repeatedly in each frame until a new value is loaded. In upstream direction, the P can
read the received 8-bit value whenever required, no interrupts being generated.
The “pre-processed channel” option must always be applied to two consecutive time
slots. The first of these time slots must have an even time slot number. If two time slots
are declared as “pre-processed channels”, the first one can be accessed by the
monitor/feature control handler, which gives access to the frame via a 16-byte FIFO.
Although this function is mainly intended for IOM- or SLD-applications, it could also be
used to transmit or receive a “burst” of data to or from a 64-kbit/s channel. The second
pre-processed time slot, the odd one, is also accessed by the
direction a 4-, 6- or 8-bit static value can be transmitted. In upstream direction the
received 8-bit value can be read. Additionally, a change detection mechanism will
generate an interrupt upon a change in any of the selected 4, 6 or 8 bits.
Pre-processed channels are usually programmed after Control Memory (CM) reset
during device initialization. Resetting the CM sets all CFI time slots to unassigned
channels (CM code “0000”). Of course, pre-processed channels can also be initialized
or re-initialized in the operational phase of the device.
Semiconductor Group
P Transfer
P can write a static 8-bit value to a downstream time slot which is then transmitted
basis.
39
Operational Description
P. In downstream
PEB 2055
PEF 2055