PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 129

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

1 is being transmitted. For unassigned channels (e.g. control memory code “0000”) the
EPIC transmits a logical 1. The maximum output current at a low voltage level of 0.45 V
is 7 mA, pull-up resistors down to 680
If programmed as tristate drivers (OMDR:COS = 0), logical 0s and 1s are transmitted
with push-pull output drivers, whereas unassigned channels are set to high impedance.
Since for each CFI time slot there is only one control memory location, only one
subchannel may be mapped to each CFI time slot. The remaining bits of such a partly
unused CFI time slot are inactive e.g. set to high impedance if OMDR:COS = 0.
Note that if an odd numbered CFI time slot is initialized as an IOM channel with switched
D channel, SC#1 … SC#0 must be set to “00” because the D channel is located at bits
7 … 6. In this case the remaining bits can still be used for C/I and monitor channel
applications (refer to chapter 5.5).
For more detailed information on subchannel switching refer to chapter 5.4.2.
CFI Standby Mode OMDR:CSB
In standby mode (OMDR:CSB = 0), the CFI output ports are set to high impedance and
the clock signals DCL and FSC, if programmed as outputs (CMD1:CSS = 0), are
switched off.
Note that the internal operation of the EPIC is not affected in standby mode, i.e. the
received CFI data is still read in and may still be processed by the EPIC (switched to
PCM or P, etc.)
In operational mode (OMDR:CSB = 1), the CFI output pins take over the function
programmed in the control memory and DCL and FSC deliver clock and framing output
signals (if CMD1:CSS = 0) as programmed in CMD1 and CMD2.
CFI Output Driver Selection OMDR:COS
The output drivers at the configurable interface (DD# or I/O#) can be programmed as
open drain or tristate drivers.
If programmed as open drain drivers (OMDR:COS = 1), external pull-up resistors
(connected to
Semiconductor Group
V
DD
) are required in order to pull the output line to a high level if a logical
can thus be used.
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Application Hints
PEB 2055
PEF 2055