PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 161

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

interface (PCM
(MAAR contains the encoding for the upstream CFI time slot (U/D = 1)). If the data
should also be transmitted at TxD#, the tristate field of that PCM time slot can be set to
low impedance (transparent loop). If TxD# should be disabled, the tristate field of that
PCM time slot can be set to high impedance (non-transparent loop).
The second connection switches the “upstream” PCM time slot (contents of the
upstream data memory) back to the downstream CFI time slot. This connection is
programmed by using exactly the same MADR value as has been used for the first
connection, i.e. the encoding for the spare upstream PCM time slot (with U/D = 1). This
MADR value is written to the downstream CM (MAAR contains the encoding for the
downstream CFI time slot (U/D = 0).
The following example illustrates the necessary programming steps for establishing CFI
to CFI loops.
5.4.3
Loops between time slots (or even subtime slots) of the CFI (CFI
possible to establish individual loops for individual time slots on both interfaces without
making external connections. These loops can serve for test purposes only or for real
switching applications within the system. It should be noted that such a loop connection
is always carried out over the opposite interface i.e. looping back a CFI time slot to
another CFI time slot occupies a spare upstream PCM time slot and looping back a PCM
time slot to another PCM time slot occupies a spare downstream and upstream CFI time
slot. The required time slot on the opposite interface can however be switched to high
impedance in order not to disturb the external line.
5.4.3.1 CFI - CFI Loops
For looping back a time slot of a CFI input port to a CFI output port, two connections must
be programmed:
A first connection switches the upstream CFI time slot to a spare PCM time slot. This
connection is programmed like a normal CFI to PCM link, i.e the MADR contains the
encoding for the upstream PCM time slot (U/D = 1) which is written to the upstream CM
Semiconductor Group
Loops
PCM) can easily be programmed in the control memory. It is thus
161
Application Hints
CFI) or the PCM
PEB 2055
PEF 2055