PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 229

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

Based on these PCM and CFI timing requirements, the following EPIC initialization
values for the PCM and CFI registers are recommended:
EPIC
PBNR = 1111 1111
POFD = 1111 0000
POFU = 0001 1000
PCSR = 0000 0001
CMD1 = 0010 0000
CMD2 = 1101 0000
CBNR = 1111 1111
Figure 80
Typical IOM
PMOD = 0010 0000
Semiconductor Group
®
PFS
PDC
TxD#
RxD#
FSC
DCL
DD#
DU#
®
-2 Line Card Timing
TS31, Bit 0
TS31,
TS31,
TS31, Bit 0
Bit 0
Bit 0
B
B
B
B
B
B
B
B
= 20
= FF
= F0
= 18
= 01
= 20
= D0
= FF
TS0,
TS0, Bit 7
TS0, Bit 7
TS0,
Bit 7
H
H
H
H
H
H
H
H
Bit 7
TS0, Bit 6
TS0,
PCM mode 0, double rate clock, PFS evaluated
with falling clock edge, PCM comparison disabled
256 bits (32 ts) per PCM frame
PFS marks downstream PCM TS0, bit 7
PFS marks upstream PCM TS0, bit 7
PCM data received with falling, transmitted with
rising clock edge
PDC/PFS clock source, PFS evaluated with falling
clock edge, prescaler = 1, CFI mode 0
FC mode 6, double rate clock, CFI data
transmitted with rising, received with falling clock
edge
256 bits (32 ts) per CFI frame
TS0,
TS0, Bit 6
Bit 6
229
Bit 6
TS0, Bit 5
TS0,
TS0,
TS0, Bit 5
Bit 5
Bit 5
TS0, Bit 4
TS0,
TS0,
TS0, Bit 4
Bit 4
Bit 4
Application Hints
ITT08096
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PEB 2055
PEF 2055