PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 126

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

If for example the upstream CFI time slot 0 of port 0 shall be switched to a PCM time slot,
the CM address 88
The complete value for CBSR is: CBSR = 04
CFI Receive Line Selection CMD1:CIS1 … CIS0
The CFI transmit line of a given logical port (as it is used for programming the switching
function) is always assigned to a dedicated physical transmit pin, e.g. in CFI mode 1, pin
DD1 carries the CFI data of logical port 1.
In receive direction however, an assignment between logical and physical ports can be
made in CFI modes 1 and 2. This selection is programmed via the alternative input
selection bits 1 and 0 (CIS1, CIS0) in the CMD1 register.
In CFI mode 0 and 3, CIS1 and CIS0 should both be set to 0.
In CFI mode 1, CIS0 selects between receive lines DU0 and DU2 for logical port 0 and
CIS1 between the receive lines DU1 and DU3 for logical port 1.
In CFI mode 2, CIS0 selects between the receive lines DU0 and DU2, CIS1 should be
set to 0.
From this it follows that:
CTAR:TSN6 … 0 = TSN + 2 = 5 + 2 = 7
The upstream CFI frame shall be shifted by 28 bits to the right (ts 4, bit 1 - 28 bits yields
in TS0, bit 5)
Since it is not possible to shift the upstream frame with respect to the downstream frame
by more than 15 bits when using the CBSR:CUS bits, the following trick must be used:
The CBSR:CUS bits are set to “0100” to shift the frame by 4 bits to the left. The
remaining shift to the right of 28 + 4 = 32 bits (equivalent to 4 time slots) can now be
performed by renumbering the upstream CFI time slots in the software. This results in
an offset of 4 time slots when addressing a CFI time slot via the Control Memory (CM):
If CFI time slot N shall be switched (N refers to the external time slot numbering), the CM
must be written with the CFI address (N + 4)
Finally the CMD2 register bits must be set to
FC2 … 0 = XXX, COC = X, CXF = 0, CRR = 1, CBN9 … 8 = 00, i.e.: CMD2 = 04
Semiconductor Group
H
(CFI p 0, TS4) must be used.
D
= 0000111
126
mod 32
H
.
B
; i.e. CTAR = 07
Application Hints
H
PEB 2055
PEF 2055
H