PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 233

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

CEPT (2.048 Mbit/s) or the T1 (1.544 Mbit/s) standards. For both standards a common
backplane data rate of 2.048 or 4.096 Mbit/s can be selected to simplify the connection
to the PBX internal PCM highway, which usually consists of 32 or 64 time slots.
Digital trunk lines require a clock recovery from the received data stream such that the
PBX clock system is locked up with the CO clock system. The examples given in the
following chapters show how to deal with these points.
5.9.2.1 PBX With Multiple ISDN Trunk Lines
In a trunk unit special attention must be given to the clock synchronization. The PBX
clock generator must deliver a stable free running clock as long as no external calls are
active. When an external call is established, the CO must be taken as reference to
synchronize the local PBX clock system.
The Siemens S
for this kinds of applications: In the LT-T (Line Termination at the T-reference point)
mode, they deliver a clock signal that is synchronous to the incoming S-frame. This clock
signal can be taken to synchronize the PCM clocks of the EPIC by means of a XTAL
controlled PLL circuit. Since the EPIC generates the IOM-2 clocks for the connected
layer-1 and layer
a frame wander and jitter between the IOM-2 and the S-frame can be tolerated up to a
certain extent. The maximum ‘wander’ value is device specific. For the SBCX, for
example, 50 s of frame deviation are internally compensated. If this value is exceeded,
a frame slip occurs that is reported to the P by a ‘slip’ indication in the C/I code. If a
frame slip occurs, the data of an S-frame may be lost or transferred twice. The slip
indications can be evaluated for statistical purposes. However, in a final design with
optimized PLL tracking, slips should not occur during normal operation of the PBX.
Since the S
For large PBXs, with many external lines, one or several Primary Rate ISDN (PRI)
connections are more advantageous. If the European CEPT standard is used, each PRI
connection provides 30 B channels of 64 kbit/s each and one D channel of 64 kbit/s. The
FALC54 can be used to implement the Primary Rate S
LT-T mode, only 1 device may be selected to deliver the reference clock. The PBX
software must determine an active line by evaluating the C/I indications of the layer-1
devices in order to select an appropriate clock source for the PLL. If several external
lines are active, any of these lines can be taken, since the CO lines are synchronous
among each other.
The layer-1 devices have a built-in frame buffer that compensates the phase offset that
may persist between the IOM-2 frame and the S
physically possible to connect a PBX trunk line together with other PBX trunk lines, or
with normal ISDN terminals, to a common S-bus, the trunk lines must also follow the
D-channel access procedure specified for ISDN terminals. This D-channel access
procedure is implemented in the QUAT-S, ISAC-S and SBCX devices and can optionally
Semiconductor Group
0
interface allows bus configurations for terminals (TEs), and since it is
0
-layer-1 transceivers SBC, SBCX, QUAT-S and ISAC-S are prepared
-
2 devices, the loop is closed. If several layer-1 devices are operated in
233
0
-frame. This buffer is ‘elastic’, such that
2m
interface according to the
Application Hints
PEB 2055
PEF 2055