PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 72

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

Semiconductor Group
4.2.5.2 MF-Channel Subscriber Address Register (MFSAR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
The exchange of monitor data normally takes place with only one subscriber circuit at a
time. This register serves to point the MF handler to that particular CFI time slot.
MFTC1..0
SAD5..0
CFI time slot encoding of MFSAR derived from MAAR:
MAAR:MA7 selects between upstream and downstream CM blocks. This information is
not required since the transfer direction is defined by CMDR (transmit or receive).
MAAR:MA0 selects between even and odd time slots. This information is also not
required since MF channels are always located on even time slots.
MFSAR: MFTC1 MFTC0 SAD5
bit 7
MFTC1
MAAR:
MFTC0
MF Channel Transfer Control 1..0; these bits, in addition to CMDR:MFT1,0
and OMDR:MFPS control the MF channel transfer as indicated in table 5.
Subscriber address 5..0; these bits define the addressed subscriber. The
CFI time slot encoding is similar to the one used for Control Memory
accesses using the MAAR register (tables 3 and 4):
H
MA7
SAD5
MA6
SAD4
SAD4
MA5
72
SAD3
SAD3 SAD2 SAD1 SAD0
MA4
write
write
Detailed Register Description
MA3
SAD2
MA2
address: A
OMDR:RBS = 0
address: 14
SAD1
MA1
PEB 2055
PEF 2055
H
bit 0
H
SAD0
MA0