PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 76

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

Semiconductor Group
4.2.6.4 Command Register (CMDR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Writing a logical 1 to a CMDR register bit starts the respective operation.
ST
TIG
CFR
MFT1..0
MFSO
bit 7
0
Start Timer.
0… no action. If the timer shall be stopped, the TIMR register must simply be
1… starts the timer to run cyclically from 0 to the value programmed in
Timer Interrupt Generation.
0… setting the TIG bit to logical 0 together with the CMDR:ST bit set to logical
1… setting the TIG bit to logical 1 together with CMDR:ST bit set to logical 1
CIFIFO Reset.
0… no action.
1… resets the signaling FIFO within 2 RCL periods, i.e. all entries and the
MF channel Transfer Control Bits 1, 0; these bits start the monitor transfer
enabling the contents of the MFFIFO to be exchanged with the subscriber
circuits as specified in MFSAR. The function of some commands depends
furthermore on the selected protocol (OMDR:MFPS). Table 5 summarizes all
available MF commands.
MF channel Search On.
0… no action.
1… the EPIC- starts to search for active MF channels. Active channels are
ST
written with a random value.
TIMR:TVAL6..0.
1 disables the interrupt generation.
causes the EPIC to generate a periodic interrupt (ISTA:TIN) each time
the timer expires.
ISTA:SFI bit are cleared.
characterized by an active MX bit (logical 0) sent by the remote
transmitter. If such a channel is found, the corresponding address is
stored in MFAIR and an ISTA:MAC-interrupt is generated. The search is
stopped when an active MF channel has been found or when
OMDR:OMS0 is set to 0.
H
TIG
CFR
76
MFT1
write
write
Detailed Register Description
MFT0
address: D
OMDR:RBS = 0
address: 1A
MFSO
PEB 2055
PEF 2055
H
bit 0
H
MFFR