PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 80

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

Semiconductor Group
4.2.6.7 Operation Mode Register (OMDR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
OMS1..01 Operational Mode Selection; these bits determine the operation mode of the
bit 7
OMS1
EPIC according to the following table:
OMS1..0 Function
00
10
11
01
OMS0
H
The CM reset mode is used to reset all locations of the control
memory code and data fields with a single command within only
256 RCL cycles. A typical application is resetting the CM with the
command MACR = 70
to all data field locations and the code ’0000’ (unassigned
channel) to all code field locations. A CM reset should be made
after each hardware reset. In the CM-reset mode the EPIC does
not operate normally i.e. the CFI- and PCM-interfaces are not
operational.
The CM initialization mode allows fast programming of the
control memory since each memory access takes a maximum of
only 2.5 RCL cycles compared to the 9.5 RCL cycles in the
normal mode. Accesses are performed on individual addresses
specified by MAAR. The initialization of control/signaling
channels in IOM or SLD applications can for example be carried
out in this mode. In the CM initialization mode the EPIC does also
not work normally.
In the normal operation mode the CFI and PCM interfaces are
operational. Memory accesses performed on single addresses
(specified by MAAR) take 9.5 RCL cycles. An initialization of the
complete data memory tristate field takes 1035 RCL cycles.
In test mode the EPIC sustains normal operation. However
memory accesses are no longer performed on a specific address
defined by MAAR, but on all locations of the selected memory,
the contents of MAAR (including the U/D bit!) being ignored. A
test mode access takes 2057 RCL cycles.
PSB
PTL
80
H
which writes the contents of MADR (xx
COS
read/write
read/write
Detailed Register Description
MFPS
OMDR:RBS = X
address: 1E
address: F
CSB
PEB 2055
PEF 2055
H
bit 0
H
/3E
RBS
H
H
)