PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 31

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

2.5
The EPIC supports the monitor/feature control and control/signalling channels according
to SLD or IOM-2 interface protocol.
The monitor handler controls the data flow on the monitor/feature control channel either
with or without an active handshake protocol. To reduce the dynamic load of the CPU a
16-byte transmit/receive FIFO is provided.
The signaling handler supports different schemes (D-channel + C/I-channel, 6-bit
signaling, 8-bit signaling).
In downstream direction the relevant content of the control memory is transmitted in the
appropriate CFI time slot. In the case of centralized ISDN D-channel handling, a
16-kbit/s D-channel received at the PCM-interface is included.
In upstream direction the signaling handler monitors the received data. Upon a change
it generates an interrupt, the channel address is stored in the 9-byte deep C/I FIFO and
the actual value is stored in the control memory. In 6-bit and 8-bit signaling schemes a
double last look check is provided.
.
2.6
– Synchronous transfer.
– 7-bit hardware timer.
– Frame length checking.
– Alternative input functions.
Semiconductor Group
This utility allows the synchronous P-access to two independent channels on the
PCM or CFI interface. Interrupts are generated to indicate the appropriate access
windows.
The timer can be used to cyclically interrupt the CPU, to determine the double last look
period, to generate a proper CFI-multiframe synchronization signal or to generate a
defined RESIN pulse width.
The PFS period is internally checked against the programmed frame length.
In PCM mode 1 and 2, the unused ports can be used for redundancy purposes. In
these modes, for every active input port a second input port exists which can be
connected to a redundant PCM line. Additionally the two lines are checked for
mismatches.
Pre-processed Channels, Layer-1 Support
Special Functions
31
Functional Description
PEB 2055
PEF 2055