PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 234

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

PEB 2055
PEF 2055
Application Hints
be set. If not required, the D-channel can also be sent transparently. If the QUAT-S is
used together with the IDEC as layer-2 controller, the IDEC must be informed about the
availability of the D-channel at the T-interface. The QUAT-S provides an enable signal
at pin DRDY that carries this information during the D-channel time slot. This signal can
be connected to the collision data input (CDR) of the IDEC to enable or disable HDLC
transmission. The IDEC must then be programmed to the ‘slave mode’ in order to
evaluate the CDR pin.
Figure 82 illustrates a complete PBX trunk card, where the EPIC controls up to
8 QUAT-S devices connected to up to 4 IOM-2 ports. On each IOM-2 port 2 IDECs take
care of the D-channel processing. The CDR input lines of the IDECs are connected with
the DRDY output pins of the QUAT-S. This is to stop the HDLC controllers in case of a
D-channel collision on the T-bus. The QUAT-S devices must be programmed via the
monitor channel to deliver appropriate Stop/Go information at pin DRDY. The 1.536 MHz
reference clock outputs (pin CLK1) of the QUAT-Ss are fed via a multiplexer to the PBX
clock generator. The P controls the multiplexer as required by the state of the lines.
Semiconductor Group
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