PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 135

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

– Access to the Control Memory Code Field: set-up of CFI time slot functionality
In the following chapters, these commands are explained in more detail.
5.3.3.1 Access to the Data Memory Data Field
The data memory (DM) data field buffers the PCM data transmitted (upstream block) and
received (downstream block) via the PCM interface. Normally this data is switched
transparently from or to the CFI and there is no need to access it from the P interface.
For some applications however it is useful to have a direct P access to the PCM frame.
When an upstream PCM time slot (or even subtime slot) is not switched from the CFI
(unassigned channel), it is possible to write a fixed value to the corresponding DM data
field location. This value will then be transmitted repeatedly in each PCM frame without
further P interaction (PCM idle code). If instead a continuous pattern should be sent,
the write access can additionally be synchronized to the frame by means of synchronous
transfer interrupts (see chapter 5.7).
Writing to an upstream DM data field location can also be restricted to a 2 or 4 bit subtime
slot. It is thus possible to have certain subtime slots of the same 8 bit time slot switched
from the CFI with the other subtime slots containing a PCM idle code. This restriction is
made via the Memory Operation Code (refer to table 22).
For test purposes the upstream DM data field contents can also be read back.
The downstream DM data field cannot be written to, it can only be read. Reading such
a location reflects the PCM data contained in the received PCM frame regardless of a
connection to the CFI having been established or not. The P can thus determine the
contents of received PCM time slots simply by reading the corresponding downstream
DM locations. This reading can, if required, also be synchronized to the frame by means
of synchronous transfer interrupts.
5.3.3
The memory access commands can be divided into the following four categories:
– Access to the Data Memory Data Field: P access to PCM frame
– Access to the Data Memory Code Field: PCM tristate control
– Access to the Control Memory Data Field: time slot assignment, P access to CFI
Semiconductor Group
frame
Memory Access Commands
135
Application Hints
PEB 2055
PEF 2055