PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 203

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

PEB 2055
PEF 2055
Application Hints
This command can also be used to perform a receive only operation: if a message shall
be received without transmission (e.g. after an active monitor channel has been found)
the transmit + receive command is issued with an empty MFFIFO.
The command is applicable for both handshake and non-handshake protocols. Since the
transfer operation is performed on the same time slot, its use is intended for IOM
applications:
– IOM-2, handshake facility enabled:
The contents of the MFFIFO is sent to the subscriber circuit subject to the IOM-2 protocol
i.e each byte must be acknowledged before the next one is sent. When the MFFIFO is
empty, the EPIC starts to receive the incoming data bytes, each byte being
autonomously acknowledged by the EPIC. Up to 16 bytes may be stored in the MFFIFO.
When the end of message is detected (MX bit inactive during two consecutive frames),
the transfer is considered terminated and an ISTA:MFFI interrupt is generated. The P
can then fetch the message from the MFFIFO. In order to determine the length of the
arrived message, the STAR:MFFE bit (MFFIFO Empty) should be evaluated before each
read access to the MFFIFO. After all bytes have been read, the MFFIFO must be reset
with the CMDR:MFFR command in order to enable new monitor transfer operations.
Semiconductor Group
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