PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 261

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

Figure 100
EPIC
Semiconductor Group
CTAR
TSN0..6 = (number of time slots + 2) the DU and DD frame is left shifted relative to frame
CBSR
CDS2..0: CFI Downstream/Upstream Bit Shift
CSCR
SC3 0..1 control port 3 (+ port 7 for CFI mode 3 (SLD))
SC2 0..1 control port 2 (+ port 6 for CFI mode 3 (SLD))
SC1 0..1 control port 1 (+ port 5 for CFI mode 3 (SLD))
SC0 0..1 control port 0 (+ port 4 for CFI mode 3 (SLD))
for 64 kBit/s channel: 00/01/10/11 = bits 7..0
for 32 kBit/s channel: 00/10 = bits 7..4,
®
start (see also CBSR)
Shift DU and DD frame:
Relative to PFS (if CMD1:CSS = 0)
Relative to FSC (if CMD1:CSS = 1)
Initialization Register Summary (working sheet)
0
0
000 = 2 bits right
001 = 1 bit right
010 = 6 bits left
011 = 5 bits left
100 = 4 bits left
101 = 3 bits left
110 = 2 bits left
111 = 1 bit left
CS3
CFI Time Slot Adjustment Register RW, 32
CFI Bit Shift Register
CFI Subchannel Register
01/11 = bits 3..0
CDS2..0
CS2
261
RW, 34
RW, 36
TSN
CS1
H
H
H
(9
(A
(A
H
H
H
+ RBS = 1), reset-val. = 00
+ RBS = 1), reset-val. = 00
+ RBS = 1), reset-val. = 00
CUS3..0
CS0
PEB 2055
PEF 2055
Appendix