PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 223

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

Interrupt Status Register
ISTA:
The ISTA register should be read after an interrupt in order to determine the interrupt
source. In connection with the hardware timer one maskable (MASK) interrupt bit is
provided by the EPIC:
TIN:
Status Register
STAR:
The STAR register bits do not generate interrupts and are not modified by reading
STAR.
TAC:
5.8.2
To simplify the realization of redundant PCM transmission lines, the EPIC can be
programmed to compare the contents of certain pairs of its PCM input lines. If a pair of
lines carry the same information (normal case), nothing happens. If however the two
lines differ in at least one bit (error case), the EPIC generates an ISTA:PIM interrupt and
indicates in the PICM register the pair of input lines and the time slot number that caused
that mismatch.
The comparison function is carried out between the pairs of physical PCM input lines
RxD0/RxD1 and RxD2/RxD3. It can be activated in all PCM modes, including PCM
mode 0. However, a redundant PCM input line that can be switched over to by means of
the PMOD:AIS1 … 0 bits is of course only available in PCM modes 1 and 2.
Semiconductor Group
PCM Input Comparison
bit 7
bit 7
MAC
TIN
Timer Interrupt; if this bit is set to logical 1, a timer interrupt previously
requested with CMDR:ST,TIG = 1 has occurred. The TIN bit is reset
by reading ISTA. It should be noted that the interrupt generation is
periodic, i.e. unless stopped by writing to TIMR, the ISTA:TIN will be
generated each time the timer expires.
Timer Active; While the timer is running (CMDR:ST=1) the TAC bit is
set to logical 1. The TAC bit is reset to logical 0 after the timer has
been stopped (W:TIMR = XX).
TAC
SFI
MFFI
PSS
MFTO
MAC
223
read/write reset value:
read
MFAB
PFI
reset value:
MFAE
PIM
Application Hints
MFRW
SIN
00
05
PEB 2055
H
H
PEF 2055
bit 0
bit 0
MFFE
SOV