PEF 2054 N V2.1 Infineon Technologies, PEF 2054 N V2.1 Datasheet - Page 79

• Manufacturer Part Number: PEF 2054 N V2.1
• Description: IC INTERFACE CTRLR PCM LCC-44
• Manufacturer: Infineon Technologies
• Series: EPICr

Specifications of PEF 2054 N V2.1

• Function: PCM Interface Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 9.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC
• Includes: Board Controller, Channel Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF2054NV2.1XT; PEF2054NV21XK; SP000057916; SP000075438

Access in multiplexed P-interface mode:
A logical 1 disables the corresponding interrupt as described in the ISTA-register.
A masked interrupt is stored internally and reported in ISTA immediately if the mask is
released. However, an SFI interrupt is also reported in ISTA if masked. In this case no
interrupt is generated. When writing register MASK while ISTA indicates a non masked
interrupt INT is temporarily set into the inactive state.
SIN
SOV
4.2.6.6 Mask Register (MASK)
Access in demultiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
TIN
Synchronous transfer Interrupt; The SIN interrupt is enabled if at least one
synchronous transfer channel (A and/or B) is enabled via the STCR:TAE,
TBE bits. The SIN interrupt is generated when the access window for the P
opens. After the occurrence of the SIN interrupt the P can read and/or write
the synchronous transfer data registers (STDA, STDB). The SIN bit is reset
by reading ISTA.
Synchronous transfer Overflow; The SOV interrupt is generated if the P fails
to access the data registers (STDA, STDB) within the access window. The
SOV bit is reset by reading ISTA.
SFI
H
MFFI
MAC
79
PFI
write
write
Detailed Register Description
PIM
address: 1C
address: E
OMDR:RBS = 0
SIN
PEB 2055
PEF 2055
H
bit 0
H
SOV