UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 603

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

Third
edition
Edition
Addition of description of internal feedback resistor and oscillation
stabilization time select register (OSTS) in 7.3 Clock Generator
Control Registers
Modification of Figure 8-1 Block Diagram of 16-Bit Timer/Event
Counter 0
Modification of Tables 8-2 TI00/TO0/P70 Pin Valid Edge and CR00,
CR01 Capture Trigger and 8-3 TI01/P71 Pin Valid Edge and CR00
Capture Trigger in 2nd edition to Table 8-2 CR00 Capture Trigger
and Valid Edges of TI00 and TI01 Pins and Table 8-3 CR01
Capture Trigger and Valid Edge of TI00 Pin (CRC02 = 1)
Modification of description procedure of each function in 8.4
Operation of 16-Bit Timer/Event Counter 0
Addition of Figure 8-26 PPG Output Configuration Diagram and
Figure 8-27 PPG Output Operation Timing
Addition of 8.5 Program List
Modification of 8.6 (3) Capture register data retention timing and
addition of (11) STOP mode or main system clock stop mode
setting
Modification of Figures 9-1 Block Diagram of 8-Bit Timer/Event
Counter 50 and 9-2 Block Diagram of 8-Bit Timer/Event Counter
51
Deletion of Caution in Figures 9-5 Format of 8-Bit Timer Mode
Control Register 50 (TMC50) and 9-6 Format of 8-Bit Timer Mode
Control Register 51 (TMC51)
Addition of [Setting] in 9.4.2 External event counter operation
Addition of description of frequency to [Setting] in 9.4.3 Square-
wave output (8-bit resolution) operation
Addition of description of cycle and duty ratio to [Setting] in 9.4.4
8-bit PWM output operation
Addition of 9.5 Program List
Deletion of 9.5 (2) Operation after compare register change
during timer count operation in 2nd edition
Deletion of oscillation stabilization time select register (OSTS) from
11.3 Registers to Control Watchdog Timer in 2nd edition
Modification of Figure 12-1 Block Diagram of Clock Output/Buzzer CHAPTER 12 CLOCK OUTPUT/
Output Controller
Modification of description in 13.2 (3) Sample & hold circuit, (4)
Voltage comparator, and addition of (10) ADTRG pin
Addition of Table 13-2 Sampling Time and A/D Conversion Start
Delay Time of A/D Converter
Deletion of 13.6 (4) Noise countermeasures (contents of deletion
are added to Figure 13-18 Example of Connecting Capacitor to
AV
Source Impedance Is High), and addition of (14) Input impedance
of ANI0 to ANI7 pins
Modification of Table 13-3 Resistances and Capacitances of
Equivalent Circuit (Reference Values)
REF
Pin and Figure 13-20 Example of Connection If Signal
Revision from Previous Edition
APPENDIX E REVISION HISTORY
User’s Manual U14046EJ5V0UD
CHAPTER 7 CLOCK GENERATOR
CHAPTER 8 16-BIT TIMER/EVENT
COUNTER 0
CHAPTER 9 8-BIT TIMER/EVENT
COUNTERS 50, 51
CHAPTER 11 WATCHDOG TIMER
BUZZER OUTPUT CONTROLLER
CHAPTER 13 8-BIT A/D CONVERTER
( PD780024A, 780024AY SUBSERIES)
Applied to:
(3/5)
601