UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 479

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

Instruction Mnemonic
16-bit
operation
Multiply/
divide
Increment/
decrement
Rotate
BCD
adjust
Bit
manipu-
late
Group
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
2. When an area except the internal high-speed RAM area is accessed
ADDW
SUBW
CMPW
MULU
DIVUW
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
ROR4
ROL4
ADJBA
ADJBS
MOV1
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
register (PCC).
AX, #word
AX, #word
AX, #word
X
C
r
saddr
r
saddr
rp
rp
A, 1
A, 1
A, 1
A, 1
[HL]
[HL]
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
Operands
CHAPTER 24 INSTRUCTION SET
User’s Manual U14046EJ5V0UD
Byte
3
3
3
2
2
1
2
1
2
1
1
1
1
1
1
2
2
2
2
3
3
2
3
2
3
3
2
3
2
Note 1
16
25
10
10
6
6
6
2
4
2
4
4
4
2
2
2
2
4
4
6
–
4
–
6
6
–
4
–
6
Clock
12 + n + m
12 + n + m
8 + n + m
Note 2
7 + n
–
–
–
–
–
–
6
–
6
–
–
–
–
–
–
–
–
7
7
–
7
8
8
–
8
AX, CY
AX, CY
AX – word
AX
AX (Quotient), C (Remainder)
r
(saddr)
r
(saddr)
rp
rp
(CY, A
(CY, A
(CY
(CY
A
(HL)
A
(HL)
Decimal Adjust Accumulator after
Addition
Decimal Adjust Accumulator after
Subtract
CY
CY
CY
CY
CY
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
3 – 0
3 – 0
3 – 0
7 – 4
r + 1
r – 1
rp + 1
rp – 1
A
7
0
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
A
A
CY
CPU
(HL)
(HL)
0
7
CY
, A
, A
X
(saddr) + 1
(saddr) – 1
AX + word
AX – word
A
A
CY
(HL)
(HL)
) selected by the processor clock control
CY
0
7
7
0
3 – 0
7 – 4
, A
, A
CY
7 – 4
3 – 0
, (HL)
, (HL)
m – 1
m + 1
CY, A
CY, A
Operation
7 – 4
3 – 0
m – 1
m + 1
A
A
m
m
)
)
A
A
1 time
1 time
3 – 0
3 – 0
A
A
m
m
)
)
,
,
AX
1 time
1 time
C
Z AC CY
Flag
477