UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 536

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

(3) Serial interface (T
534
SCL0 clock frequency
Bus free time
(between stop and start conditions)
Hold time
SCL0 clock low-level width
SCL0 clock high-level width
Start/restart condition setup time
Data hold time CBUS-compatible master
Data setup time
SDA0 and SCL0 signal rise time
SDA0 and SCL0 signal fall time
Stop condition setup time
Spike pulse width controlled by input filter
Capacitive load per bus line
Notes 1. In the start condition, the first clock pulse is generated after this hold time.
CHAPTER 26 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS: f
(f) I
Note 1
2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide
3. If the device does not extend the SCL0 signal low hold time (t
4. The high-speed mode I
5. Cb: Total capacitance per bus line (unit: pF)
2
C bus mode ( PD780024AY, 780034AY Subseries only)
Parameter
at least 300 ns of hold time for the SDA0 signal (which is V
t
conditions described below must be satisfied.
• If the device does not extend the SCL0 signal low state hold time
• If the device extends the SCL0 signal low state hold time
HD:DAT
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (t
= 1000 + 250 = 1250 ns by standard mode I
I
2
t
C bus
SU:DAT
needs to be fulfilled.
A
= 40 to +85 C, V
250 ns
2
C bus is available in a standard mode I
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
Cb
DD
CLK
BUF
HD:STA
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
F
SU:STO
SP
User’s Manual U14046EJ5V0UD
= 1.8 to 5.5 V) (3/3)
0
250
Note 2
MIN.
4.7
4.0
4.7
4.0
4.7
5.0
4.0
0
Standard Mode
2
C bus specification).
1000
MAX.
100
300
400
IHmin
LOW
20 + 0.1Cb
20 + 0.1Cb
. of the SCL0 signal).
), only the maximum data hold time
2
100
C bus system. At this time, the
0
MIN.
Note 2
1.3
0.6
1.3
0.6
0.6
0.6
High-Speed Mode
0
Note 4
0
X
Note 5
Note 5
= 1.0 TO 8.38 MHz)
0.9
MAX.
300
300
400
400
50
Note 3
Rmax
. + t
Unit
kH
SU:DAT
pF
ns
ns
ns
ns
s
s
s
s
s
s
s
s
Z