UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 363

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

(5) Stop condition detection
18.5.8 Address match detection method
address.
address has been set to slave address register 0 (SVA0) and when the address set to SVA0 matches the slave address
sent by the master device, or when an extension code has been received.
18.5.9 Error detection
0 (IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0
data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared
data values do not match.
18.5.10 Extension code
In I
Address match can be detected automatically by hardware. An interrupt request (INTIIC0) occurs when a local
In I
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code flag (EXC0)
(2) If “111110
Note EXC0: Bit 5 of IIC status register 0 (IICS0)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
INTIIC0 is generated when a stop condition is detected.
2
2
C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by IIC shift register
C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
is set for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge of the eighth
clock. The local address stored in slave address register 0 (SVA0) is not affected.
the results are as follows. Note that INTIIC0 occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC0 = 1
• Seven bits of data match:
code, such processing is performed by software.
For example, after the extension code is received, if you do not wish to operate the target device as a slave
device, you can set bit 6 (LREL0) of IIC control register 0 (IICC0) to 1 to set the standby mode for the next
communication operation.
COI0: Bit 4 of IIC status register 0 (IICS0)
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
” is set to SVA0 by a 10-bit address transfer and “111110
Slave Address
0000
0000
0000
0000
1111
000
000
001
010
0
Table 18-3. Extension Code Bit Definitions
R/W Bit
0
1
COI0 = 1
User’s Manual U14046EJ5V0UD
General call address
Start byte
CBUS address
Address that is reserved for different bus format
10-bit slave address specification
Note
Note
Description
” is transferred from the master device,
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