UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 189

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

Symbol
Address: FF60H
TMC0
Cautions 1. To write different data to TMC0, stop the timer operation before writing.
Remarks 1. TO0:
Notes 1. Set the valid edge of the TI00/TO0/P70 pin with prescaler mode register 0 (PRM0).
TMC03 TMC02
OVF0
7
0
2. If the clear & start mode entered on a match between TM0 and CR00 is selected, when the set value
0
0
1
1
0
1
2. TI00:
3. TM0:
4. CR00: 16-bit timer capture/compare register 00
5. CR01: 16-bit timer capture/compare register 01
2. The timer operation must be stopped before writing to bits other than the OVF0 flag.
of CR00 is FFFFH and the TM0 value changes from FFFFH to 0000H, the OVF0 flag is set to 1.
6
0
Overflow not detected
Overflow detected
Figure 8-2. Format of 16-Bit Timer Mode Control Register 0 (TMC0)
0
1
0
1
After reset: 00H
5
0
16-bit timer/event counter 0 output pin
16-bit timer/event counter 0 input pin
16-bit timer counter 0
Operation stop
(TM0 cleared to 0)
Free-running mode
Clear & start on TI00 valid
edge
Clear & start on match between
TM0 and CR00
and clear mode selection
4
0
Note 1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0
Operating mode
TMC03
<3>
R/W
TMC02
<2>
Note 2
Overflow detection of 16-bit timer counter 0 (TM0)
User’s Manual U14046EJ5V0UD
1
0
OVF0
<0>
No change
Match between TM0 and
CR00 or match between
TM0 and CR01
Match between TM0 and
CR00 or match between
TM0 and CR01
TO0 output timing selection
Generated on match
between TM0 and CR00, or
match between TM0 and
CR01
Not generated
Interrupt request generation
187