UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 362

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

18.5.7 Interrupt request (INTIIC0) generation timing and wait control
and the corresponding wait control, as shown in Table 18-2.
(1) During address transmission/reception
(2) During data reception
(3) During data transmission
(4) Wait cancellation method
360
WTIM0
The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated
Notes 1. The slave device’s INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when
Remark The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and
0
1
• Slave device operation:
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
The four wait cancellation methods are as follows.
• By setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1
• By writing to the IIC shift register 0 (IIC0)
• By setting a start condition (setting bit 1 (STT0) of IICC0 to 1)
• By setting a stop condition (setting bit 0 (SPT0) of IICC0 to 1)
Note Master only.
When an 8-clock wait has been selected (WTIM0 = 0), the output level of ACK must be determined prior to wait
cancellation.
2. If the received address does not match the contents of slave address register 0 (SVA0) and extension
9
9
wait control are both synchronized with the falling edge of these clock signals.
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
there is a match with the address set to slave address register 0 (SVA0).
At this point, ACK is output regardless of the value set to IICC0’s bit 2 (ACKE0). For a slave device
that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIIC0 is generated at the falling of the 9th clock,
but wait does not occur.
code is not received, neither INTIIC0 nor a wait occurs.
Address
Notes 1, 2
Notes 1, 2
During Slave Device Operation
Data Reception
8
9
Table 18-2. INTIIC0 Timing and Wait Control
Note 2
Note 2
Interrupt and wait timing are determined depending on the conditions described in
Notes 1 and 2 above, regardless of the WTIM0 bit.
the WTIM0 bit.
User’s Manual U14046EJ5V0UD
Data Transmission
8
9
Note 2
Note 2
Address
9
9
Note
Note
During Master Device Operation
Data Reception
8
9
Data Transmission
8
9