UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 438

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

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21.2.2 STOP mode
(1) STOP mode setting and operating statuses
Item
Clock generator
CPU
Ports (output latches)
16-bit timer/event counter 0
8-bit timer/event counters 50, 51
Watch timer
Clock output
Buzzer output
A/D converter
Serial interface
External interrupt
Bus line during
external expansion
Watchdog timer
The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.
Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V
The operating statuses in the STOP mode are described below.
2. Because the interrupt request signal is used to clear the standby mode, if there is an
Other than UART0
UART0
STOP Mode Setting
to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode
in a system where an external clock is used for the main system clock.
interrupt source with the interrupt request flag set and the interrupt mask flag reset, the
standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode
immediately after execution of the STOP instruction. The operating mode is set after the
wait set using the oscillation stabilization time select register (OSTS).
AD0 to AD7
A8 to A15
ASTB
WR, RD
WAIT
Table 21-3. STOP Mode Operating Statuses
CHAPTER 21 STANDBY FUNCTION
Only main system clock oscillation is stopped.
Operation stops.
Status before STOP mode setting is held.
Operation stops.
Operable only when TI50, TI51 are selected as count clock.
Operable only when f
count clock.
Operation stops.
Operable when f
output clock.
BUZ is at low level.
Operation stops.
Operable only when externally supplied clock is specified as the serial clock.
Operation stops. (Transmit shift register 0 (TXS0), receive shift register 0 (RX0),
and receive buffer register 0 (RXB0) hold the value just before the clock stopped.)
Operable
High impedance
Status before STOP mode setting is held.
Low level
High level
High impedance
User’s Manual U14046EJ5V0UD
With Subsystem Clock
XT
is selected as
XT
is selected as
Operation stops.
PCL is at low level.
Without Subsystem Clock
DD1
via a pull-up resistor