UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 358

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

18.5.4 Acknowledge (ACK) signal
receives an ACK signal after transmitting 8 bits of data. However, when the master device is the receiving device,
it does not output an ACK signal after receiving the final data to be transmitted. The transmitting device detects whether
or not an ACK signal is returned after it transmits 8 bits of data. When an ACK signal is returned, the reception is
judged as normal and processing continues. If the slave device does not return an ACK signal, the master device
outputs either a stop condition or a restart condition and then stops the current transmission. Failure to return an
ACK signal may be caused by the following two factors.
(normal receive response).
to be set. When this TRC0 bit’s value is “0”, it indicates receive mode. Therefore, ACKE0 should be set to 1.
after receiving several bytes, setting ACKE0 to 0 will prevent the master device from starting transmission of the
subsequent data.
either a restart condition or a stop condition should therefore be output, setting ACKE0 to 0 will prevent the ACK signal
from being returned. This prevents the MSB data from being output via the SDA0 line (i.e., stops transmission) during
transmission from the slave device.
eighth clock regardless of the ACKE0 value. No ACK signal is output if the received address is not a local address.
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The acknowledge (ACK) signal is used by the transmitting and receiving devices to confirm serial data reception.
The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device normally
(a) Reception was not performed normally.
(b) The final data was received.
When the receiving device sets the SDA0 line to low level during the ninth clock, the ACK signal becomes active
When bit 2 (ACKE0) of IIC control register 0 (IICC0) is set to 1, automatic ACK signal generation is enabled.
Transmission of the eighth bit following the 7 address data bits causes bit 3 (TRC0) of IIC status register 0 (IICS0)
When the slave device is receiving (when TRC0 = 0), if the slave device does not need to receive any more data
Similarly, when the master device is receiving (when TRC0 = 0) and the subsequent data is not needed and when
When the local address is received, an ACK signal is automatically output in sync with the falling edge of the SCL0’s
The ACK signal output method during data reception is based on the wait timing setting, as described below.
• When 8-clock wait is selected: ACK signal is output when ACKE0 is set to 1 before wait cancellation.
• When 9-clock wait is selected: ACK signal is automatically output at the falling edge of the SCL0’s eighth clock
(WTIM0 = 0)
(WTIM0 = 1)
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
SDA0
SCL0
if ACKE0 has already been set to 1.
A6
1
Figure 18-14. ACK Signal
User’s Manual U14046EJ5V0UD
A5
2
A4
3
A3
4
A2
5
A1
6
A0
7
R/W ACK
8
9