UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 403

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

Interrupt
Non-
maskable
Maskable
Software
Notes 1. The default priority is the priority applicable when two or more maskable interrupts are generated
Type
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 19-1.
Priority
Default
simultaneously. 0 is the highest priority, and 18 is the lowest.
10
11
12
13
14
15
16
17
18
0
1
2
3
4
5
6
7
8
9
Note 1
INTWTI
INTWDT
INTWDT
INTP0
INTP1
INTP2
INTP3
INTSER0
INTSR0
INTST0
INTCSI30
INTCSI31
INTIIC0
INTTM00
INTTM01
INTTM50
INTTM51
INTAD0
INTWT
INTKR
BRK
Name
Reference time interval signal from watch timer
Watchdog timer overflow
(with watchdog timer mode 1 selected)
Watchdog timer overflow
(with interval timer mode selected)
Pin input edge detection
Serial interface UART0 reception error
generation
End of serial interface UART0 reception
End of serial interface UART0 transmission
End of serial interface SIO30 transfer
End of serial interface SIO31 transfer
[only for PD780024A, 780034A Subseries]
End of serial interface IIC0 transfer
[only for PD780024AY, 780034AY Subseries]
Match between TM0 and CR00
(when CR00 is specified as compare register)
Detection of TI00 or TI01 valid edge
(when CR00 is specified as capture register)
Match between TM0 and CR01
(when CR01 is specified as compare register)
Detection of TI00 valid edge
(when CR01 is specified as capture register)
Match between TM50 and CR50
Match between TM51 and CR51
End of A/D converter conversion
Watch timer overflow
Port 4 falling edge detection
BRK instruction execution
CHAPTER 19 INTERRUPT FUNCTIONS
Table 19-1. Interrupt Source List
Interrupt Source
User’s Manual U14046EJ5V0UD
Trigger
Internal/
External
Internal
External
Internal
External
Address
0004H
0006H
0008H
000AH
000CH
0010H
0014H
0016H
0018H
001AH
001CH
001EH
0020H
0022H
0026H
0028H
003EH
000EH
0012H
0024H
Vector
Table
Configuration
Type
Basic
(C)
(D)
(A)
(B)
(B)
(E)
Note 2
401