UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 347

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

Note This flag’s signal is invalid when IICE0 = 0.
This bit’s setting is invalid during an address transfer and is valid after the transfer is completed. When in master
mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that
has received a local address, a wait is inserted at the falling edge of the ninth clock after an ACK signal is issued.
When the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 = 0)
• Cleared by instruction
• When RESET is input
Condition for clearing (ACKE0 = 0)
• Cleared by instruction
• When RESET is input
ACKE0
WTIM0
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
0
1
0
1
Interrupt request is generated at the eighth clock’s falling edge.
Master mode:
Slave mode:
Interrupt request is generated at the ninth clock’s falling edge.
Master mode:
Slave mode:
Disable acknowledgment.
Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level. However,
the ACK is invalid during address transfers and is valid when EXC0 = 1.
Figure 18-5. Format of IIC Control Register 0 (IICC0) (2/4)
After output of eight clocks, clock output is set to low level and wait is set.
After input of eight clocks, the clock is set to low level and wait is set for master device.
After output of nine clocks, clock output is set to low level and wait is set.
After input of nine clocks, the clock is set to low level and wait is set for master device.
Note
Note
User’s Manual U14046EJ5V0UD
Control of wait and interrupt request generation
Acknowledgment control
Condition for setting (WTIM0 = 1)
• Set by instruction
Condition for setting (ACKE0 = 1)
• Set by instruction
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