UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 415

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

19.4.2 Maskable interrupt request acknowledgment operation
(MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if
interrupts are enabled (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged
during servicing of a higher priority interrupt request (when the ISP flag is reset to 0).
neither non-maskable interrupt requests nor maskable interrupt requests are acknowledged.
19-3 below.
by the priority specification flag is acknowledged first. If two or more interrupt requests have the same priority level,
the request with the highest default priority is acknowledged first.
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP flag. Further, the vector table data determined for each interrupt request is loaded
into the PC and branched.
A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask
Moreover, even if the EI instruction is executed during execution of a non-maskable interrupt servicing program,
The times from generation of a maskable interrupt request until interrupt servicing is performed are listed in Table
For the interrupt request acknowledgment timing, see Figures 19-11 and 19-12.
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.
Remark 1 clock: 1/f
If two or more interrupt requests are generated simultaneously, the request with a higher priority level specified
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 19-10 shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
Return from an interrupt is possible using the RETI instruction.
Table 19-3. Times from Generation of Maskable Interrupt Until Servicing
When
When
CPU
(f
CPU
PR = 0
PR = 1
: CPU clock)
CHAPTER 19 INTERRUPT FUNCTIONS
User’s Manual U14046EJ5V0UD
7 clocks
8 clocks
Minimum Time
32 clocks
33 clocks
Maximum Time
Note
413