UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 357

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

18.5.2 Addresses
to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique
address.
data matches the data values stored in slave address register 0 (SVA0). If the address data matches the SVA0 values,
the slave device is selected and communicates with the master device until the master device transmits a start
condition or stop condition.
direction specification below, are together written to IIC shift register 0 (IIC0) and are then output. Received
addresses are written to IIC0.
18.5.3 Transfer direction specification
transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting data to a slave
device. When the transfer direction specification bit has a value of “1”, it indicates that the master device is receiving
data from a slave device.
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
The slave address and the eighth bit, which specifies the transfer direction as described in 18.5.3 Transfer
The slave address is assigned to the higher 7 bits of IIC0.
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
operation.
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
INTIIC0
INTIIC0
SDA0
SCL0
SDA0
SCL0
Figure 18-13. Transfer Direction Specification
A6
A6
1
1
User’s Manual U14046EJ5V0UD
A5
A5
Figure 18-12. Address
2
2
A4
A4
3
3
Address
A3
A3
4
4
A2
A2
5
5
Transfer direction specification
A1
A1
6
6
A0
A0
7
7
R/W
R/W
8
8
9
9
Note
Note
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