UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 352

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

350
Remark LREL0: Bit 6 of IIC control register 0 (IICC0)
Condition for clearing (ACKD0 = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• When RESET is input
Condition for clearing (STD0 = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• When RESET is input
Condition for clearing (SPD0 = 0)
• At the rising edge of the address transfer byte’s
• When IICE0 changes from 1 to 0 (operation stop)
• When RESET is input
ACKD0
STD0
SPD0
following address transfer
first clock following setting of this bit and
detection of a start condition
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
0
1
0
1
0
1
IICE0:
ACK was not detected.
ACK was detected.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect.
Stop condition was not detected.
Stop condition was detected. The master device’s communication was terminated and the bus was
released.
Bit 7 of IIC control register 0 (IICC0)
Figure 18-6. Format of IIC Status Register 0 (IICS0) (3/3)
User’s Manual U14046EJ5V0UD
Detection of start condition
Detection of stop condition
Detection of ACK
Condition for setting (ACKD0 = 1)
• After the SDA0 line is set to low level at the
Condition for setting (STD0 = 1)
• When a start condition is detected
Condition for setting (SPD0 = 1)
• When a stop condition is detected
rising edge of the SCL0’s ninth clock