UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 249

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

(2) Watchdog timer mode register (WDTM)
Address: FFF9H
Symbol
WDTM
Caution
This register sets the watchdog timer operating mode and enables/disables counting.
WDTM is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Notes 1. Once set to 1, RUN cannot be cleared to 0 by software.
Remark
2. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software.
3. The watchdog timer starts operation as an interval timer when RUN is set to 1.
Thus, once counting starts, it can only be stopped by RESET input.
: Don’t care
When RUN is set to 1 so that the watchdog timer is cleared, the actual overflow time is up to
2
WDTM4
8
RUN
RUN
/f
<7>
0
1
0
1
1
X
seconds shorter than the time set by the watchdog timer clock select register (WDCS).
Figure 11-3. Format of Watchdog Timer Mode Register (WDTM)
After reset: 00H
Count stop
Counter is cleared and counting starts
WDTM3
6
0
0
1
Interval timer mode
(Maskable interrupt request occurs upon generation of overflow)
Watchdog timer mode 1
(Non-maskable interrupt request occurs upon generation of overflow)
Watchdog timer mode 2
(Reset operation is activated upon generation of overflow)
CHAPTER 11 WATCHDOG TIMER
R/W
5
0
User’s Manual U14046EJ5V0UD
Watchdog timer operation mode selection
Watchdog timer operation mode selection
WDTM4
4
Note 3
WDTM3
3
2
0
Note 1
Note 2
1
0
0
0
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