UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 346

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

Address: FFA8H After reset: 00H
344
Symbol
IICC0
Note This flag’s signal is invalid when IICE0 = 0.
Condition for clearing (IICE0 = 0)
• Cleared by instruction
• When RESET is input
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0)
• Automatically cleared after execution
• When RESET is input
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status
(TRC0 = 1), the SDA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0)
• Automatically cleared after execution
• When RESET is input
Condition for clearing (SPIE0 = 0)
• Cleared by instruction
• When RESET is input
WREL0
LREL0
SPIE0
IICE0
IICE0
<7>
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
0
1
0
1
0
1
0
1
Stop operation. Reset IIC status register 0 (IICS0). Stop internal operation.
Enable operation.
Normal operation
This exits from the current communications operation and sets standby mode. This setting is
automatically cleared after being executed. Its uses include cases in which a locally irrelevant
extension code has been received.
The SCL0 and SDA0 lines go into the high impedance state.
The following flags of IIC status register 0 (IICS0) and IIC control register 0 (IICC0) are cleared.
• STD0 • ACKD0
Do not cancel wait
Cancel wait. This setting is automatically cleared after wait is canceled.
Disable
Enable
LREL0
<6>
Figure 18-5. Format of IIC Control Register 0 (IICC0) (1/4)
Enable/disable generation of interrupt request when stop condition is detected
WREL0
R/W
<5>
Note
• TRC0 • COI0 • EXC0 • MSTS0 • STT0 • SPT0
Note
Note
User’s Manual U14046EJ5V0UD
SPIE0
<4>
Exit from communications
I
WTIM0
2
C operation enable
<3>
Cancel wait
Condition for setting (IICE0 = 1)
• Set by instruction
Condition for setting (LREL0 = 1)
• Set by instruction
Condition for setting (WREL0 = 1)
• Set by instruction
Condition for setting (SPIE0 = 1)
• Set by instruction
ACKE0
<2>
STT0
<1>
SPT0
<0>