UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 349

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

Caution
Note Set SPT0 only in master mode. However, SPT0 must be set and a stop condition generated before the
Remark Bit 0 (SPT0) becomes 0 when it is read after data setting.
Cautions concerning set timing
• For master reception:
• For master transmission:
• Cannot be set at the same time as STT0.
• SPT0 can be set only when in master mode.
• When WTIM0 has been set to 0, if SPT0 is set during the wait period that follows output of eight clocks, note
Condition for clearing (SPT0 = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• When RESET is input
first stop condition is detected following the switch to the operation enabled status. For details, see 18.5.14
Other cautions.
SPT0
that a stop condition will be generated during the high level period of the ninth clock.
When a ninth clock must be output, WTIM0 should be changed from 0 to 1 during the wait period following
output of eight clocks, and SPT0 should be set during the wait period that follows output of the ninth clock.
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
0
1
When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set during the ninth clock
and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to high impedance.
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to
high level. Next, after the rated amount of time has elapsed, the SDA0 line changes from low level
to high level and a stop condition is generated.
Figure 18-5. Format of IIC Control Register 0 (IICC0) (4/4)
Cannot be set during transfer.
Can be set only in the waiting period when ACKE0 has been set to 0 and slave has
been notified of final reception.
A stop condition cannot be generated normally during the ACK0 period. Therefore,
set it during the waiting period.
User’s Manual U14046EJ5V0UD
Note
Stop condition trigger
Condition for setting (SPT0 = 1)
• Set by instruction
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