UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 281

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

14.2 A/D Converter Configuration
(1) Successive approximation register (SAR)
(2) A/D conversion result register 0 (ADCR0)
(3) Sample & hold circuit
The A/D converter consists of the following hardware.
Caution
This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from
the series resistor string, and holds the result from the most significant bit (MSB).
When up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are transferred to
A/D conversion result register 0 (ADCR0).
This is a 16-bit register that stores the A/D conversion results. The lower 6 bits are fixed to 0. Each time A/
D conversion ends, the conversion result is loaded from the successive approximation register (SAR) and held
by this register. The most significant bit (MSB) is stored in ADCR0 first. The higher 8 bits of the conversion results
are stored in FF17H. The lower 2 bits of the conversion results are stored in FF16H.
ADCR0 is read by a 16-bit memory manipulation instruction.
RESET input clears ADCR0 to 0000H.
The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D
conversion is started and holds the sampled analog input voltage value during A/D conversion.
Symbol
ADCR0
When A/D converter mode register 0 (ADM0) and analog input channel specification register
0 (ADS0) are written, the contents of ADCR0 may become undefined. Read the conversion
result following conversion completion before writing to ADM0 and ADS0. Using a timing
other than the above may cause an incorrect conversion result to be read.
CHAPTER 14 10-BIT A/D CONVERTER ( PD780034A, 780034AY SUBSERIES)
Address: FF16H, FF17H
Analog input
Hardware trigger
input
Registers
Control registers
Figure 14-2. Format of A/D Conversion Result Register 0 (ADCR0)
Item
Table 14-1. A/D Converter Configuration
FF17H
8 channels (ANI0 to ANI7)
1 (ADTRG)
Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)
A/D converter mode register 0 (ADM0)
Analog input channel specification register 0 (ADS0)
User’s Manual U14046EJ5V0UD
After reset: 0000H
Configuration
R
0
0
FF16H
0
0
0
0
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