UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 482

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

480
Instruction Mnemonic
Condi-
tional
branch
CPU
control
Group
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
2. When an area except the internal high-speed RAM area is accessed
BT
BF
BTCLR
DBNZ
SEL
NOP
EI
DI
HALT
STOP
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
register (PCC).
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
B, $addr16
C, $addr16
saddr, $addr16
RBn
Operands
CHAPTER 24 INSTRUCTION SET
User’s Manual U14046EJ5V0UD
Byte
3
4
3
3
3
4
4
3
4
3
4
4
3
4
3
2
2
3
2
1
2
2
2
2
Note 1
10
10
10
10
10
8
–
8
–
–
8
–
–
8
–
6
6
8
4
2
–
–
6
6
Clock
12 + n + m
11 + n
11 + n
Note 2
11
11
11
11
12
12
12
10
9
–
9
–
–
–
–
–
–
6
6
–
–
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
then reset (saddr.bit)
PC
then reset sfr.bit
PC
then reset A.bit
PC
then reset PSW.bit
PC
then reset (HL).bit
B
PC
C
PC
(saddr)
PC
RBS1, 0
No Operation
IE
IE
Set HALT Mode
Set STOP Mode
B – 1, then
C –1, then
1 (Enable Interrupt)
0 (Disable Interrupt)
PC + 3 + jdisp8 if (saddr.bit) = 1
PC + 4 + jdisp8 if sfr.bit = 1
PC + 3 + jdisp8 if A.bit = 1
PC + 3 + jdisp8 if PSW.bit = 1
PC + 3 + jdisp8 if (HL).bit = 1
PC + 4 + jdisp8 if (saddr.bit) = 0
PC + 4 + jdisp8 if sfr.bit = 0
PC + 3 + jdisp8 if A.bit = 0
PC + 4 + jdisp8 if PSW.bit = 0
PC + 3 + jdisp8 if (HL).bit = 0
PC + 4 + jdisp8 if (saddr.bit) = 1
PC + 4 + jdisp8 if sfr.bit = 1
PC + 3 + jdisp8 if A.bit = 1
PC + 4 + jdisp8 if PSW.bit = 1
PC + 3 + jdisp8 if (HL).bit = 1
PC + 2 + jdisp8 if B
PC + 2 + jdisp8 if C
PC + 3 + jdisp8 if(saddr)
CPU
(saddr) – 1, then
) selected by the processor clock control
n
Operation
0
0
0
Z AC CY
Flag