UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 435

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

21.2 Standby Function Operations
21.2.1 HALT mode
(1) HALT mode setting and operating statuses
Clock generator
CPU
Ports (output latches) Status before HALT mode setting is held.
16-bit timer/event
counter 0
8-bit timer/event
counters 50, 51
Watch timer
Watchdog timer
Clock output
Buzzer output
A/D converter
Serial interface
External interrupt
Bus line
during
external
expansion
Item
Notes 1. Including case when external clock is not supplied.
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the
subsystem clock.
The operating statuses in the HALT mode are described below.
HALT Mode
2. Including case when external clock is supplied.
AD0 to AD7 High impedance
A8 to A15 Status before HALT mode setting is held.
ASTB
WR, RD
WAIT
Setting
Both main system clock and subsystem clock can be oscillated. Clock supply to CPU stops.
Operation stops.
Operable
Operable
Operable when f
selected as count clock.
Operable
Operable when f
is selected as output clock.
Operable
Stop
Operable
Operable
Low level
High level
High impedance
Without Subsystem
Clock
HALT Instruction Execution When
Using Main System Clock
Note 1
Table 21-1. HALT Mode Operating Statuses
X
X
to f
/2
CHAPTER 21 STANDBY FUNCTION
7
X
is
/2
7
User’s Manual U14046EJ5V0UD
Operable
Operable
With Subsystem
Clock
Note 2
Operation stops.
With Main System
Clock Oscillation
HALT Instruction Execution When
Using Subsystem Clock
Stop
Operable when TI50,
TI51 are selected as
count clock.
Operable when f
selected as count clock.
Operable when f
selected as output clock.
BUZ is at low level.
Operable during
external clock input.
With Main System
Clock Oscillation
Stopped
XT
XT
is
is
433