HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 8

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

This LSI is a microcomputer (MCU) made up of the H8S/2000 CPU with Renesas Technology's
original architecture as its core, and the peripheral functions required to configure a system, eg PC
server.
The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a
16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward
compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the transition
from the H8/300, H8/300L, or H8/300H to the H8S/2000 CPU.
This LSI is equipped with ROM, RAM, two kinds of PWM timers (PWM and PWMX), a 16-bit
free running timer (FRT), an 8-bit timer (TMR), a watchdog timer (WDT), a serial communication
interface (SCI), an I
converter, and I/O ports as on-chip peripheral modules required for system configuration.
A data transfer controller (DTC) is included as a bus master.
A flash memory (F-ZTAT
The CPU and ROM are connected to a 16-bit bus, enabling byte data and word data to be accessed
in a single state. This improves the instruction fetch and process speeds.
Two operating modes are provided, offering a choice of address space and single chip
mode/external extended mode. Boot programming into a flash memory, on-chip emulation, and
boundary scan can be selected as special operating modes.
Note: * F-ZTAT
Target Users: This manual was written for users who use this LSI in the design of application
Objective:
Notes on reading this manual:
• In order to understand the overall functions of the chip
Rev. 3.00, 03/04, page vi of xl
Read this manual in the order of the table of contents. This manual can be roughly categorized
into the descriptions on the CPU, system control functions, peripheral functions and electrical
characteristics.
systems. Target users are expected to understand the fundamentals of electrical
circuits, logic circuits, and microcomputers.
This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
TM
2
C bus interface (IIC), an LPC interface (LPC), a D/A converter, an A/D
is a trademark of Renesas Technology Corp.
TM
*) version is available for this LSI’s 256, 384, and 512-kbyte ROM.
Preface