HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 745
HD64F2168VTE33
Manufacturer Part Number
HD64F2168VTE33
Description
Manufacturer
Renesas Electronics America
Datasheet
1.HD64F2168VTE33.pdf
(876 pages)
Specifications of HD64F2168VTE33
Cpu Family
H8S
Device Core Size
16/32Bit
Frequency (max)
33MHz
Interface Type
I2C/IrDA/SCI
Program Memory Type
Flash
Program Memory Size
256KB
Total Internal Ram Size
40KB
# I/os (max)
106
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant
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21.3.2
SDBPR is a 1-bit shift register. In BYPASS, CLAMP, or HIGHZ mode, SDBPR is connected
between the ETDI and ETDO pins.
21.3.3
SDBSR is a shift register provided on the PAD for controlling the I/O terminals of this LSI.
Using EXTEST mode or SAMPLE/PRELOAD mode, a boundary scan test conforming to the
IEEE1149.1 standard can be performed.
Table 21.3 shows the relationship between the terminals of this LSI and the boundary scan
register.
Bypass Register (SDBPR)
Boundary Scan Register (SDBSR)
Rev. 3.00, 03/04, page 703 of 830
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