HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 520

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

15.4.5
In I
data, and the slave device returns an acknowledge signal.
The slave device operates as the device specified by the master device when the slave address in
the first frame following the start condition that is issued by the master device matches its own
address.
Rev. 3.00, 03/04, page 478 of 830
(master output)
(master output)
(slave output)
User processing
SCL
SDA
2
SDA
ICDR
IRTR
IRIC
C bus format slave receive mode, the master device outputs the transmit clock and transmit
Figure 15.16 Stop Condition Issuance Timing Example in Master Receive Mode
Data 2
Slave Receive Operation
Bit 0
8
[3]
[4] IRTR=0
Data 1
[6] IRIC clear
(to end wait
insertion)
A
[4] IRTR=1
[7] Set ACKB=1
9
[8] Wait for one clock pulse
[3]
Bit 7
[9] Set TRS=1
1
[10] ICDR read (Data 2)
(MLS = ACKB = 0, WAIT = 1)
Bit 6
2
Bit 5
3
Data 3
[11] IRIC clear
Data 2
Bit 4
4
Bit 3
5
Bit 2
6
Bit 1
7
Bit 0
8
[13] IRTR=0
[12]
[14] IRIC clear
(to end wait
insertion)
A
[15] WAIT cleared to 0,
[12]
[13] IRTR=1
9
IRIC clear
Data 3
[16] ICDR read
Stop condition generation
(Data 3)
[17] Stop condition issuance