HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 541

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Notes: 1. Does not meet the I
7. Notes on ICDR register read at end of master reception
Item
t
SDAHO
To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1
and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is
high, and generates the stop condition. After this, receive data can be read by means of an
ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to
ICDR, and so it will not be possible to read the second byte of data.
If it is necessary to read the second byte of data, issue the stop condition in master receive
mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the
BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the
bus has been released, then read the ICDR register with TRS cleared to 0.
Note that if the receive data (ICDR data) is read in the interval between execution of the
instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the
actual generation of the stop condition, the clock may not be output correctly in subsequent
master transmission.
Clearing of the MST bit after completion of master transmission/reception, or other
modifications of IIC control bits to change the transmit/receive operating mode or settings,
must be carried out during interval (a) in figure 15.29 (after confirming that the BBSY bit has
been cleared to 0 in the ICCR register).
2. Value when the IICXn bit is set to 1. When the IICXn bit is cleared to 0, the value is
3.
t
Indi-
cation
3 t
cyc
cyc
The values in the above table will vary depending on the settings of the bits TCSS,
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
IICX5 to IICX0 and CKS0 to CKS2. Depending on the frequency it may not be possible
to achieve the maximum transfer rate; therefore, whether or not the I
specifications are met must be determined in accordance with the actual setting
conditions.
(– 6t
Calculated using the I
speed mode: 1300 ns min.).
cyc
) (n = 0 to 5).
Standard
mode
High-speed
mode
t
Influence
(Max.)
0
0
Sr
2
/t
C bus interface specification. Remedial action such as the following
Sf
2
C bus specification values (standard mode: 4700 ns min.; high-
Time Indication (at Maximum Transfer Rate) [ns]
I
Specifi-
cation
(Min.)
0
0
2
C Bus
φ =
5 MHz
600
600
φ =
8 MHz
375
375
300
300
φ =
10
MHz
Rev. 3.00, 03/04, page 499 of 830
188
188
φ =
16
MHz
150
150
φ =
20
MHz
2
C bus interface
120
120
φ =
25
MHz
91
91
φ =
33
MHz