HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 623

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

16.4.7
A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a
host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the
serialized interrupt transfer cycle generated by the host or a supporting function, and a request
signal is generated by the frame corresponding to that interrupt. The timing is shown in figure
16.10.
The serialized interrupt transfer cycle frame configuration is as follows. Two of the states
comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level
at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The
recover state must be driven by the host or slave processor that was driving the preceding state.
LCLK
SERIRQ
Drive source
LCLK
SERIRQ
Drive source
H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample, I = Idle
LPC Interface Serialized Interrupt Operation (SERIRQ)
IRQ14 frame
S
IRQ1
None
SL
or
H
R
T
START
Host controller
Start frame
H
IRQ15 frame
S
IRQ15
Figure 16.10 SERIRQ Timing
R
R
T
IOCHCK frame
T
S
None
S
IRQ0 frame
R
None
R
T
T
I
S
IRQ1 frame
IRQ1
Host controller
Stop frame
Rev. 3.00, 03/04, page 581 of 830
STOP
H
R
T
R
S
IRQ2 frame
T
None
R
Next cycle
T
START